Power management systems require the power semiconductor devices to have low on-resistance and low parasitic capacitance to reduce device conduction losses and switching losses. Power metal oxide semiconductor (MOS) devices are characterized in their gate drive with low power consumption, fast switching speed, easy to be connected in parallel, etc. Owing to these characteristics, the power MOS devices are widely used in the power management systems. B. J. Baliga, in U.S. Pat. No. 5,998,833, reported a structure of a split-gate deep trench MOS device, as shown in FIG. 1. According to the structure disclosed, a split-gate electrode is used to shield the capacitive coupling between the control gate electrode and the epitaxial layer of the device to reduce the gate-to-drain parasitic capacitance Cgd. The structure of the split-gate deep trench MOS device not only reduces the Cgd introduced by the overlap of the gate field plate and the epitaxial layer in the MOS device with step oxide, but also retains the assistant depletion effect on the epitaxial layer from the gate field plate. Therefore, the split-gate deep trench MOS device has a lower gate charge Qg and no degeneration on the on-resistance Ron, which is advantageous for improving the switching characteristics and the working efficiency of the power management system. While reducing the gate-to-drain capacitance Cgd of the device, the gate field plate connected to the source in the split-gate deep trench MOS device also introduces a parasitic capacitance Cgs between the gate and the gate field plate and a parasitic capacitance Cds between the gate field plate and the epitaxial layer, thereby increasing the input capacitance Ciss and the output capacitance Coss of the split-gate deep trench MOS device, partially offsetting the advantage of reducing the gate-to-drain capacitance Cgd for the split-gate deep trench MOS device.
Therefore, in view of the above problems, it is imperative to reduce the parasitic capacitances Cgs and Cds introduced by the gate field plates in the conventional split-gate deep trench MOS devices. The embodiments of the present invention are proposed in response to this situation.